1. Technical Field
The present invention relates to a semiconductor memory device and, more particularly, to a device and method for canceling an Inter Symbol Interference (ISI) component of a received signal.
2. Related Art
There has been a recent trend towards increasing clock frequency and data transfer rate with semiconductor technology advances. With personal computers (PC), the clock frequency of a central processing unit (CPU) has significantly evolved beyond 3 GHz while the CPU's peripheral devices data transfer rates lag behind. In dynamic random access memory (DRAM) devices, particularly, data transfer rates degrade because distortion caused by ISI that arise, in turn, because of limited channel bandwidth and multi-drop structure. Where a DRAM bus is designed to have one channel, an increase in channel loading may also limit bandwidth, thus causing ISI. This ISI may also distort a received signal and degrade the data transfer rate. Further, where the DRAM bus is configured with a multi-drop bus architecture that has a plurality of slots and discontinuous points, an originally received signal is distorted by waves reflected from other chips. The ISI due to bandwidth limitation is referred to as linear ISI. The signal distortion caused by a reflected wave in the multi-drop architecture is referred to as to nonlinear ISI. Because both the linear and nonlinear ISI cause distortion to the received signal, they are collectively called ISI.
FIG. 1 is a block diagram showing a DRAM multi-drop bus where ISI arises. FIG. 2 is a waveform diagram illustrating a received signal that is ISI modified by FIG. 1. Brief descriptions will be given with reference to these figures.
Referring to FIG. 1, the bus transmits and receives signals between the DRAM and a DRAM controller over a transmission line made of a printed circuit board (PCB). In this multi-drop bus there are two ranks in each of four slots. Where the DRAMs present in the respective ranks are shared by the same module or other modules, pin loading increases. This increase in pin loading causes ISI because of reflected waves received from other chips, thus severely distorting transmitted data.
FIG. 2 shows a profile of a transmitted signal whose amplitude is reduced by termination resistance and which is distorted by ISI. In an environment, such as a stub-series terminated logic (SSTL) interface, the base voltage may have a non-zero value because of the termination resistance. In such a case, even though there is no ISI, a received signal is reduced in amplitude, and may contain an unnecessary ISI component due to influence from linear and nonlinear ISI.
An input buffer is usually capable of recognizing an ISI distorted signal as shown in FIG. 2. ISI distorted signal recognition advances continue. For example, a decision feedback equalizer (DFE) circuit for reducing ISI on a SSTL signal transmission line is suggested in U.S. Pat. No. 6,493,394. Similar circuits are also suggested in U.S. Pat. Nos. 6,377,637 and 6,157,688. In these circuits, however, the linear ISI and nonlinear ISI cannot be optimally canceled in the transmission system of a DRAM multi-drop bus architecture including an SSTL interface. This is because these circuits address reducing ISI on transmission lines.